Structure and method for lead free solder electronic package interconnections

ABSTRACT

An electronic package having a solder interconnect liquidus temperature hierarchy to limit the extent of the melting of the C4 solder interconnect during subsequent second level join/assembly and rework operations. The solder hierarchy employs the use of off-eutectic solder alloys of Sn/Ag and Sn/Cu with a higher liquidus temperature for the C4 first level solder interconnections, and a lower liquidus temperature alloy for the second level interconnections. When the second level chip carrier to PCB join/assembly operations occur, the chip to chip carrier C4 interconnections do not melt completely. They continue to have a certain fraction of solids, and a lower fraction of liquids, than a fully molten alloy. This provides reduced expansion of the solder join and consequently lower stresses on the C4 interconnect.

RELATED APPLICATIONS

[0001] This application is related to subject matter described andclaimed in U.S. patent application Ser. No. 10/246,282 (attorney docketno. FIS9-2002-0017US1) entitled “Solder Hierarchy For Lead Free SolderJoint” by the inventors of the instant application.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a lead free solder structure forthe assembly of electronic components, and more particularly, to a leadfree solder hierarchy for use in the assembly of electronic components.

[0003] Current controlled collapse chip connection (C4) or “flip chip”interconnection technology for joining chips to either ceramic ororganic substrates typically employ a 97/3 Pb/Sn joining solder alloy asthe ball-limiting metallurgy (BLM) on the chip side of the interconnect,and a suitable metallization, typically Ni/Au or Cr/Cu/Ni/Au, on thesubstrate side of the interconnect. This interconnect structure has towithstand temperature cycling. This temperature cycling can be a verystringent requirement, especially for chip on board interconnects wherethe chip is attached directly to a printed circuit board (PCB).

[0004] This is because the thermal coefficient of expansion (TCE) of thechip is around 3 parts per million (ppm), and that of a typical PCB is15-18 ppm. For a ceramic substrate chip carrier, the TCE is much bettermatched, because the ceramic TCE lies in the range of 3.5 to 6.6 ppm. Anunderfill material, typically an epoxy, is often used to create a morereliable structure, particularly for chip-on-board schemes, where thestrain caused by the high TCE mismatch is accommodated without causingfails.

[0005] A current problem now facing the industry is that leadelimination is a strategic requirement for all manufacturers. A leadfree solution for chip attachment is actively being sought. One possiblesolution is to use a Sn rich alloy such as Sn/Ag/Cu or Sn/Ag/Bi, wherethe Sn comprises about 96% of the alloy. Such an alloy requires the useof a lower temperature for joining, in the range of 245 to 255° C. Thisis in contrast to temperatures as high as 340° C. for the Pb/Sn solderalloy.

[0006] An additional problem is that in manufacturing, joining the chipto a first level package, typically a ceramic or organic chip carrier,is the first step. This is followed by encapsulation with an underfillmaterial and hat/lid attachment to form a module. After this first levelinterconnect assembly is complete, the module proceeds to the secondlevel join. Second level join is the interconnect of the chip carrier toa PCB. This interconnect may be, for example, a ceramic ball grid array(CBGA), ceramic column grid array (CCGA), or plastic ball grid array(PBGA). In the Pb/Sn system, all this can be achieved easily, becausethe first level chip join to chip carrier step uses a 97/3 Pb/Sn solderalloy and requires a very high temperature, approximately 340° C. Thesecond level chip carrier to PCB join step uses lower Pb compositions,such as eutectic Pb/Sn, and requires a much lower reflow temperature inthe range of 200-220° C.

[0007] Therefore in the Pb system the chip C4 solder connection remainsmostly undisturbed and in the solid state during subsequent processing.Using a Pb free, Sn rich alloy for both first level chip join and secondlevel module to board join creates the problem of the chip BLM becomingmolten during the second level attach processes and subsequent reflowssuch as may be required for rework.

[0008] Another problem is that when the first level SnAgCu solderinterconnect becomes completely molten inside the underfill encapsulant,it produces large hydrostatic stresses on the walls of the encapsulant.These forces create strains large enough to cause delamination,cracking, rupture and finally, catastrophic fail of the encapsulantregions. This would likely cause shorting between the C4 solderconnections, and potentially cause opens where the C4 solder connectionsmay break away from their original as-joined position.

[0009] Whereas other alloy systems such as AuSn 80/20 may be employed toproduce a solder temperature hierarchy, such solutions may not be widelyapplicable because of various manufacturing problems. Examples includethe cost of the materials, brittle metallurgical properties and solderinteractions which cause stress on the chip.

[0010] Therefore, notwithstanding the prior art solutions to theproblem, there remains a need for a solder structure hierarchy whichemploys the use of alloys with a higher liquidus temperature for thefirst level C4 interconnections, and the use of alloys with a lowerliquidus temperature for second level interconnections.

[0011] Accordingly, it is a purpose of the present invention to providea lead free solder hierarchy structure for electronic packaging.

[0012] These and other purposes of the present invention will becomemore apparent after referring to the following description considered inconjunction with the accompanying drawings.

BRIEF SUMMARY OF THE INVENTION

[0013] The purposes and advantages of the present invention have beenachieved by providing a lead free solder hierarchy structure forelectronic package interconnections comprising an electronic circuitchip attached to a top side of a chip carrier with a first lead freeoff-eutectic solder composition, an array of lead free solderconnections, such as solder columns or solder balls, attached to abottom side of said chip carrier with a second lead free off-eutecticsolder composition, the second lead free off-eutectic solder compositionhaving a lower liquidus temperature than the first lead freeoff-eutectic solder composition; and a printed circuit board having atop side attached to the array of lead free solder connections by athird lead free solder composition, the third lead free soldercomposition having a lower liquidus temperature than the secondoff-eutectic lead free solder composition thereby creating a lead freehierarchy for electronic packaging interconnections.

[0014] The first chip interconnect lead free off-eutectic soldercomposition is an alloy consisting essentially of between 52.0-95.0weight % Sn, between 48.0-5.0 weight % Ag, and having inter-metallicswith a melting temperature greater than 250° C. and having dispersedgrains of SnAg inter-metallic phase structure. Preferred compositionsinclude 72.0% Sn and 28.0% Ag; 82.0% Sn and 18.0% Ag; 88.0% Sn and 12.0%Ag, and 52.0% Sn and 48.0% Ag.

[0015] Alternatively, the first chip interconnect lead free off-eutecticsolder composition may be an alloy consisting essentially of between84.0-99.3% Sn, between 16.0-0.7% Cu; and having inter-metallics with amelting temperature greater than 250° C. and having dispersed grains ofSnCu inter-metallic phase structure. Preferred compositions include84.0% Sn and 16.0% Cu; and 93.0% Sn and 7.0% Cu;

[0016] The present invention also provides a method for creating a leadfree solder melting hierarchy for first level assembly comprising thesteps of:

[0017] providing an electronic circuit chip having ball limitingmetallurgy pads on a bottom surface of the chip;

[0018] placing off-eutectic lead free solder on the ball limitingmetallurgy pads;

[0019] heating the off-eutectic lead free solder to reflow theoff-eutectic lead free solder and form off-eutectic lead free solderbumps on the ball limiting metallurgy pads;

[0020] providing a chip carrier having electrical contact pads on a topsurface of the chip carrier;

[0021] placing a lead free solder alloy in contact with the contactpads;

[0022] placing said off-eutectic lead free solder bumps in contact withthe lead free solder alloy; and heating the off-eutectic lead freesolder bumps to reflow the off-eutectic lead free solder bumps to formoff-eutectic lead free solder fillets which adhere the chip to the chipcarrier.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The features of the invention believed to be novel and theelements characteristic of the invention are set forth withparticularity in the appended claims. The Figures are for illustrationpurposes only and are not drawn to scale. The invention itself, however,both as to organization and method of operation, may best be understoodby reference to the detailed description which follows taken inconjunction with the accompanying drawings in which:

[0024]FIG. 1 is a schematic view of the lead free solder hierarchystructure for electronic package interconnections of the presentinvention.

[0025]FIG. 2 is a schematic view of a chip/boat assembly.

[0026]FIG. 3 is a schematic view of a chip with lead free solder bumpsaccording to the present invention.

[0027]FIG. 4 is a schematic view of a chip/boat/chip carrier assembly.

[0028]FIG. 5 is a schematic view of a module with heat sink.

DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention provides a solder liquidus temperaturehierarchy to limit the extent of the melting of the C4 solderinterconnect between the chip and chip carrier during subsequent secondlevel join/assembly and rework operations. The term “liquidustemperature” is defined as that temperature above which the solder alloyis in a completely liquid phase.

[0030] It is desirable to stay within the same alloy system that is usedfor other Pb-free joining operations in the module/package. TheSn—Ag—Cu, Sn—Cu or Sn—Ag systems are the most prevalent and preferredalloy systems for Pb-free interconnections and are recommended by theNational Electronics Manufacturing Initiative (NEMI).

[0031] The present invention employs the use of alloys, some combinationof two or more of Sn, Ag, Cu, with a higher liquidus temperature for theC4 first level solder interconnections, and a lower liquidus temperaturealloy for the second level interconnections. According to the presentinvention, when the second level chip carrier to PCB join/assemblyoperations occur, the chip to chip carrier C4 interconnections are notable to melt completely. They continue to have a certain fraction ofsolids, and a lower fraction of liquids, than a fully molten alloy.Therefore the expansion is curtailed so as to produce lower stresses onthe encapsulant or underfill. Depending on the maximum temperatureallowed for a homogenization reflow, and the method of deposition(plating, screening, evaporation or other), alloys homogenizing withdifferent liquidus temperatures may be employed.

[0032] In a first embodiment of the present invention a Sn/Agoff-eutectic lead free solder composition is provided having betweenabout 52.0-95.0 weight % Sn and between about 48.0-5.0 weight % Ag andhaving inter-metallics with a melting temperature greater than 250° C.The term “inter-metallic” has its ordinary meaning of a compound withtwo or more metals.

[0033] In a preferred embodiment of the present invention a 72Sn/28Ag(weight %) solder alloy is used which has a liquidus temperature ofapproximately 400° C. A chip join C4 reflow cycle with a peaktemperature of approximately 355-375° C., with adequate dwell timetypically about 1-4 minutes, will suffice to create a homogenous leadfree C4 solder alloy interconnection. A homogenized solder alloyinterconnection has a uniformly distributed inter-metallic phasestructure.

[0034] During the subsequent second level join/assembly process, themaximum peak temperature is approximately 250° C. This temperature willcreate a pasty two-phase inter-metallic structure in the C4 solder alloyinterconnect, comprised of approximately 68 weight % liquid phase, andapproximately 32 weight % solid phase. This alloy structure willrestrict the expansion of the C4 interconnections and ensure theintegrity of the surrounding encapsulant.

[0035] In another preferred embodiment of the present invention a82Sn/18Ag (in weight %) solder alloy is used which has a liquidustemperature of approximately 355° C. A chip join C4 reflow cycle with apeak temperature of approximately 355-375° C., with adequate dwell timetypically about 1-4 minutes, will completely melt the C4 solder alloyinterconnect. Then during the subsequent second level join/assemblyprocess, the maximum peak temperature is approximately 250° C. Thistemperature will create a pasty two-phase inter-metallic structure inthe C4 solder alloy interconnect, comprised of approximately 82 weight %liquid phase, and approximately 18 weight % solid phase. This alloystructure will restrict the expansion of the C4 interconnections andensure the integrity of the surrounding encapsulant.

[0036] In another preferred embodiment of the present invention a88Sn/12Ag (in weight %) solder alloy is used which has a liquidustemperature of approximately 310° C. A chip join C4 reflow cycle with apeak temperature of approximately 355-375° C., with adequate dwell timetypically about 1-4 minutes, will completely melt the C4 solder alloyinterconnect. Then during the subsequent second level join/assemblyprocess, the maximum peak temperature is approximately 250° C. Thistemperature will create a pasty two-phase inter-metallic structure inthe C4 solder alloy interconnect, comprised of approximately 91 weight %liquid phase, and approximately 9 weight % solid phase. This alloystructure will restrict the expansion of the C4 interconnections andensure the integrity of the surrounding encapsulant.

[0037] In another preferred embodiment of the present invention a52Sn/48Ag (in weight %) solder alloy is used which has a liquidustemperature of approximately 480° C. A chip join C4 reflow cycle with apeak temperature of approximately 355-375° C., with adequate dwell timetypically about 1-4 minutes, will suffice to create a homogenized C4solder alloy interconnection. Then during the subsequent second leveljoin/assembly process, the maximum peak temperature is approximately250° C. This temperature will create a pasty two-phase inter-metallicstructure in the C4 solder alloy interconnect, comprised ofapproximately 38 weight % liquid phase, and approximately 62 weight %solid phase. This alloy structure will restrict the expansion of the C4interconnections and ensure the integrity of the surroundingencapsulant.

[0038] In a second embodiment of the present invention a Sn/Cuoff-eutectic lead free solder composition of between about 84.0-99.3weight % Sn and between about 16.0-0.7 weight % Cu and havinginter-metallics with a melting temperature greater than 250° C.

[0039] In a preferred embodiment of the present invention a 84Sn/16Cu(in weight %) solder alloy is used which has a liquidus temperature ofapproximately 500° C. A chip C4 reflow cycle with a peak temperature ofapproximately 350-375° C., with adequate dwell time typically about 1-4minutes, will suffice to create a homogenized C4 solder alloyinterconnection. Then during the subsequent second level join/assemblyprocess, the maximum peak temperature is approximately 250° C. Thistemperature will create a pasty two-phase inter-metallic structure inthe C4 solder alloy interconnect, comprised of approximately 72 weight %liquid phase, and approximately 28 weight % solid phase. This alloystructure will restrict the expansion of the C4 interconnections andensure the integrity of the surrounding encapsulant.

[0040] In another preferred embodiment of the present invention a93Sn/7Cu (in weight %) solder alloy is used which has a liquidustemperature of approximately 410° C. A chip C4 reflow cycle with a peaktemperature of approximately 350-375° C., with adequate dwell timetypically about 1-4 minutes, will suffice to create a homogenized C4solder alloy interconnection. Then during the subsequent second leveljoin/assembly process, the maximum peak temperature is approximately250° C. This temperature will create a pasty two-phase inter-metallicstructure in the C4 solder alloy interconnect, comprised ofapproximately 86 weight % liquid phase, and approximately 14 weight %solid phase. This alloy structure will restrict the expansion of the C4interconnections and ensure the integrity of the surroundingencapsulant.

[0041] The present invention allows the creation of a lead free solderhierarchy structure for electronic package interconnections. Referringto FIG. 1 an electronic circuit chip 10 having BLM pads 20 on a bottomsurface is attached to a top side of a chip carrier 90 having contactpads 95. The chip 10 is joined to the chip carrier 90 with the lead freeoff-eutectic solder composition of the present invention 80. An array oflead free solder connections, such as solder columns 110 or solder balls(not shown) are then used to join the chip carrier 90 to a PCB 120.

[0042] The lead free solder connections 110 are attached to the bottomside of the chip carrier 90 with a second lead free off-eutectic soldercomposition 140 which has a lower liquidus temperature than the firstlead free off-eutectic solder composition 80. The chip carrier 90 isthen joined to a PCB 120 by a third lead free solder composition 150which has a lower liquidus temperature than the second off-eutectic leadfree solder composition 140 thereby creating a lead free hierarchy forelectronic packaging interconnections.

[0043] In a preferred embodiment of the lead free solder hierarchy thefirst lead free off-eutectic solder composition 80 is about 72.0 weight% Sn and 28.0 weight % Ag, and has dispersed grains of SnAginter-metallic phase structure and a liquidus temperature ofapproximately 400° C. The second lead free off-eutectic soldercomposition 140 is about 82.0 weight % Sn and 18 weight % Ag, and hasdispersed grains of SnAg inter-metallic phase structure and a liquidustemperature of approximately 355° C. The third lead free soldercomposition 150 is about 95.5 weight % Sn and 3.8 weight % Ag and 0.7weight % Cu and has a liquidus temperature of approximately 217° C.

[0044] A preferred method is illustrated with reference to FIG. 2. Thereis shown an electronic circuit chip 10 having BLM pads 20 on a bottomsurface 11 of the chip 10. A preform boat 30, typically made ofgraphite, contains openings 35 which are arrayed to coincide with theposition of the BLM pads 20 on the chip 10. The off-eutectic solderpreforms 40 of the present invention are then placed in the boatopenings 35. The chip 10 is then positioned on the boat 30 such that theBLM pads 20 are in contact with the off-eutectic solder preforms 40.

[0045] The resulting chip/boat assembly is then heated to the requiredreflow temperature, typically between 350° C. and 375° C., whereby thesolder preforms 40 are reflowed onto the BLM pads 20. The chip/boatassembly is then cooled resulting in the chip BLM pads 20 being coatedwith off-eutectic lead free solder bumps 50 as is illustrated in FIG. 3.

[0046] Referring now to FIG. 4 there is shown a second boat 60containing second openings 65 which are arrayed to coincide with theposition of the solder bumps 50 on the chip 10. A chip carrier 90 isprovided having contact pads 95 on a top surface 91 of the chip carrier90 such that the second openings 65 coincide with the contact pads 95. Alead free solder alloy or fluxing agent 70 is placed in the secondopenings 65 and in contact with the pads 95. The chip 10 is thenpositioned on the opposite side of the second boat 60 such that theoff-eutectic solder bumps 50 are in contact with the solder alloy orfluxing agent 70.

[0047] The resulting chip/chip carrier assembly is heated to a seconddesired reflow temperature whereby the off-eutectic solder bumps 50 arereflowed on the flux coated or lead free alloy coated contact pads. Thechip/chip carrier assembly is then cooled wherein the reflowedoff-eutectic solder bumps form off-eutectic solder fillets 80 whichadhere the chip 10 to the chip carrier as shown in FIG. 1.

[0048] Referring again to FIG. 1 the finished module is shown. Prior tojoining the chip carrier 90 to a printed circuit board (PCB) 120 anencapsulant 100 is dispensed under the chip 10. This encapsulant 100,also commonly referred to as an “underfill”, is typically an epoxy basedmaterial. It is used to improve the reliability of the solder joint byabsorbing some of the strain caused by the TCE.

[0049] The chip carrier 90 is then joined to the PCB 120 with a solderconnection 150. In FIG. 1 the solder connection is shown as a columngrid array. As shown in FIG. 5 the module may also have a heat sink 130attached either directly to the chip 10 as shown, or to a lid (notshown) positioned over the chip and attached to the chip carrier.

[0050] Referring again to FIG. 1 the solder hierarchy achieved by thepresent invention is shown. The off-eutectic solder of the presentinvention 80 will have a higher reflow temperature than the BSM fillet140. Similarly, the BSM fillet will have a higher reflow temperaturethan the PCB fillet 150. The BSM fillet 140 corresponds to theoff-eutectic lead free solder structure disclosed in related applicationSer. No. 10/246,282, and the PCB fillet is eutectic SnAgCu (SAC) soldercommon in the industry.

[0051] It will be apparent to those skilled in the art that theadditions of small amounts of a third, or even a fourth element, to thedisclosed Sn/Ag and Sn/Cu off-eutectic alloys would not effect thehierarchy structure and such additions are therefore within the scope ofthe disclosed invention. The elements added would have to readily forman inter-metallic compound with Sn as does Cu and Ag. Examples of suchelements include Bi, Sb, In, Zn and Pd. The addition of approximately0.5 weight % Sb or 0.5 weight % Bi is a preferred candidate to counterthe problem of Sn “whiskers” in relatively pure Sn alloys.

[0052] The present invention is an improvement over the prior art. Itrestricts the amount of liquid in the C4 interconnection during secondlevel reflows, thereby reducing the hydrostatic tensile forces exertedon the encapsulant. It therefore preserves the integrity of theencapsulated C4 structure and prevents delamination and electrical failsdue to shorting.

[0053] An additional advantage of the present invention is that for chipon board applications, a small amount of eutectic Sn/Ag, Sn/Cu orSn/Ag/Cu could be used, so that the chip join reflow cycle can bemaintained with a peak reflow temperature of 250° C. or less. This wouldbe applicable to the high temp/low temp Pb-free C4 solution for directchip on organic package situations.

[0054] It will be apparent to those skilled in the art having regard tothis disclosure that other modifications of this invention beyond thoseembodiments specifically described here may be made without departingfrom the spirit of the invention. Accordingly, such modifications areconsidered within the scope of the invention as limited solely by theappended claims.

What is claimed is:
 1. An off-eutectic lead free solder compositionconsisting essentially of: between 52.0-95.0 weight % Sn; between48.0-5.0 weight % Ag; and having inter-metallics with a meltingtemperature greater than 250° C.
 2. The off-eutectic lead free soldercomposition of claim 1, wherein said composition is about: 72.0 weight %Sn; 28.0 weight % Ag; and having dispersed grains of SnAg inter-metallicphase structure.
 3. The off-eutectic lead free solder composition ofclaim 1, wherein said composition is about: 82.0 weight % Sn; 18.0weight % Ag; and having dispersed grains of SnAg inter-metallic phasestructure.
 4. The off-eutectic lead free solder composition of claim 1,wherein said composition is about: 88.0 weight % Sn; 12.0 weight % Ag;and having dispersed grains of SnAg inter-metallic phase structure. 5.The off-eutectic lead free solder composition of claim 1, wherein saidcomposition is about: 52.0 weight % Sn; 48.0 weight % Ag; and havingdispersed grains of SnAg inter-metallic phase structure.
 6. Anoff-eutectic lead free solder composition consisting essentially of:between 84.0-99.3 weight % Sn; between 16.0-0.7 weight % Cu; and havinginter-metallics with a melting temperature greater than 250° C.
 7. Theoff-eutectic lead free solder composition of claim 6, wherein saidcomposition is about: 84.0 weight % Sn; 16.0 weight % Cu; and havingdispersed grains of SnCu inter-metallic phase structure.
 8. Theoff-eutectic lead free solder composition of claim 6, wherein saidcomposition is about: 93.0 weight % Sn; 7.0 weight % Cu; and havingdispersed grains of SnCu inter-metallic phase structure.
 9. A lead freesolder hierarchy structure for electronic package interconnectionscomprising: an electronic circuit chip attached to a top side of a chipcarrier with a first lead free off-eutectic solder composition; an arrayof lead free solder connections having a first end attached to a bottomside of said chip carrier with a second lead free off-eutectic soldercomposition, said second lead free off-eutectic solder compositionhaving a lower liquidus temperature than said first lead freeoff-eutectic solder composition; and a printed circuit board having atop side attached to a second side of said array of lead free solderconnections by a third lead free solder composition, said third leadfree solder composition having a lower liquidus temperature than saidsecond off-eutectic lead free solder composition thereby creating a leadfree hierarchy for electronic packaging interconnections.
 10. The leadfree solder hierarchy of claim 9 wherein said first lead freeoff-eutectic solder composition is about 72.0 weight % Sn and 28.0weight % Ag, and having dispersed grains of SnAg inter-metallic phasestructure and a liquidus temperature of approximately 400° C.; whereinsaid second lead free off-eutectic solder composition is about 82.0weight % Sn and 18 weight % Ag, and having dispersed grains of SnAginter-metallic phase structure and a liquidus temperature ofapproximately 355° C.; and wherein said third lead free soldercomposition is about 95.5 weight % Sn and 3.8 weight % Ag and 0.7 weight% Cu and has a liquidus temperature of approximately 217° C.
 11. Amethod for creating a lead free solder melting hierarchy for first levelassembly comprising the steps of; providing an electronic circuit chiphaving ball limiting metallurgy pads on a bottom surface of said chip;placing off-eutectic lead free solder on said ball limiting metallurgypads; heating said off-eutectic lead free solder to reflow saidoff-eutectic lead free solder and form off-eutectic lead free solderbumps on said ball limiting metallurgy pads; providing a chip carrierhaving electrical contact pads on a top surface of said chip carrier;placing a lead free solder alloy in contact with said contact pads;placing said off-eutectic lead free solder bumps in contact with saidlead free solder alloy; and heating said off-eutectic lead free solderbumps to reflow said off-eutectic lead free solder bumps to formoff-eutectic lead free solder fillets which adhere said chip to saidchip carrier.
 12. The method of claim 11 further comprising the step ofdispensing an encapsulant in the interface between said chip and saidchip carrier.
 13. The method of claim 11 wherein said off-eutecticsolder fillet has a composition between about 84.0 weight % Sn to 99.3weight % Sn and between about 16.0 weight % Cu to 0.7 weight % Cu andhaving inter-metallics with a melting temperature greater than 250° C.14. The method of claim 13 wherein said off-eutectic solder fillet has acomposition of about 93.0 weight % Sn, 7.0 weight % Cu and havedispersed grains of SnCu inter-metallic phase structure.
 15. The methodof claim 13 wherein said off-eutectic solder fillet has a composition ofabout 84.0 weight % Sn, 16.0 weight % Cu and have dispersed grains ofSnCu inter-metallic phase structure.
 16. The method of claim 11 whereinsaid off-eutectic solder fillet has a composition between about 52.0weight % Sn to 95.0 weight % Sn and between about 48.0 weight % Ag to7.0 weight % Ag and having inter-metallics with a melting temperaturegreater than 250° C.
 17. The method of claim 16 wherein saidoff-eutectic solder fillet has a composition of about 82.0 weight % Sn,18.0 weight % Ag and have dispersed grains of SnAg inter-metallic phasestructure.
 18. The method of claim 16 wherein said off-eutectic solderfillet has a composition of about 88.0 weight % Sn, 12.0 weight % Ag andhave dispersed grains of SnAg inter-metallic phase structure.
 19. Themethod of claim 16 wherein said off-eutectic solder fillet has acomposition of about 72 weight % Sn, 28 weight % Ag and have dispersedgrains of SnAg inter-metallic phase structure.
 20. The method of claim16 wherein said off-eutectic solder fillet has a composition of about 52weight % Sn, 48 weight % Ag and have dispersed grains of SnAginter-metallic phase structure.